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165 Publications
2009 | Conference Paper | LibreCat-ID: 13030
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.
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2008 | Misc | LibreCat-ID: 13033
Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.
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2008 | Misc | LibreCat-ID: 13035
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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2007 | Misc | LibreCat-ID: 13038
Hellebrand S. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk); 2007.
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2007 | Misc | LibreCat-ID: 13039
Ali M, Welzl M, Hessler S, Hellebrand S. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007.
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2007 | Misc | LibreCat-ID: 13042
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand S. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07). IEEE; 2007:50-58. doi:10.1109/dft.2007.43
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07). IEEE; 2007:185-190. doi:10.1109/ddecs.2007.4295278
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. In: 12th IEEE European Test Symposium (ETS’07). IEEE; 2007:91-96. doi:10.1109/ets.2007.10
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. In: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper). ; 2007.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper). 2007;37(4 (124)):212-219.
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2007 | Journal Article | LibreCat-ID: 13044
Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture. 2007;1(2):113-123.
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2007 | Conference Paper | LibreCat-ID: 13040
Ali M, Welzl M, Hessler S, Hellebrand S. A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. In: 4th International Conference on Information Technology: New Generations (ITNG’07). ; 2007:1027-1032.
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2007 | Conference Paper | LibreCat-ID: 13041
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. Test und Zuverlässigkeit nanoelektronischer Systeme. In: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2007.
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2006 | Journal Article | LibreCat-ID: 13045
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. it - Information Technology. 2006;48(5):305-311.
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2005 | Misc | LibreCat-ID: 13046
Oehler P, Hellebrand S. A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany; 2005.
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2005 | Misc | LibreCat-ID: 13101
Ali M, Welzl M, Hellebrand S. Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
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2005 | Misc | LibreCat-ID: 13102
Oehler P, Hellebrand S. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
Ali M, Welzl M, Zwicknagl M, Hellebrand S. Considerations for Fault-Tolerant Networks on Chips. In: IEEE International Conference on Microelectronics (ICM’05). IEEE; 2005. doi:10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler P, Hellebrand S. Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In: 10th IEEE European Test Symposium (ETS’05). IEEE; 2005:148-153. doi:10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali M, Welzl M, Hellebrand S. A Dynamic Routing Mechanism for Network on Chip. In: 23rd IEEE NORCHIP Conference. IEEE; 2005:70-73. doi:10.1109/norchp.2005.1596991
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing M, Ruehrup S, Schindelhauer C, et al. Sensor Networks with More Features Using Less Hardware. In: {GOR/NGB Conference Tilburg 2004}. Tilburg, Netherlands; 2004.
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2004 | Misc | LibreCat-ID: 13099
Breu R, Fahringer T, Fensel D, Hellebrand S, Middeldorp A, Scherzer O. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. OCG Journal, pp. 28-29; 2004.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand S, Wuertenberger A, S. Tautermann C. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France; 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357
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2003 | Misc | LibreCat-ID: 13098
Breu R, Hellebrand S, Welzl M. Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia; 2003.
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870
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2002 | Misc | LibreCat-ID: 13097
Hellebrand S, Wuertenberger A. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA; 2002.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.
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2002 | Journal Article | LibreCat-ID: 13070
Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.
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2001 | Misc | LibreCat-ID: 13096
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden; 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712
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2001 | Journal Article | LibreCat-ID: 13047
Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.
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2001 | Journal Article | LibreCat-ID: 13068
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.
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2000 | Misc | LibreCat-ID: 13094
Hellebrand S, Wunderlich H-J. Hardwarepraktikum Im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag; 2000.
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2000 | Misc | LibreCat-ID: 13095
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal; 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274
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1999 | Book | LibreCat-ID: 13065
Hellebrand S. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg; 1999.
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1999 | Misc | LibreCat-ID: 13093
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop; 1999.
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693
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1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.
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1998 | Report | LibreCat-ID: 13029
Hellebrand S, Wunderlich H-J. Test Und Synthese Schneller Eingebetteter Systeme. Universität Stuttgart; 1998.
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