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84 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056
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2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591
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2020 | Conference Paper | LibreCat-ID: 19421
Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.
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2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020
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2018 | Conference Paper | LibreCat-ID: 10575
Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028
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2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). IEEE; 2017. doi:10.1109/ddecs.2017.7934564
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2017 | Conference Paper | LibreCat-ID: 29463
Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced aging by design randomization. In: 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26
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2015 | Conference Paper | LibreCat-ID: 29465
Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. In: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127373
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2015 | Conference Paper | LibreCat-ID: 29466
Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting progressive age monitoring of timing variations. In: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127368
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2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014. doi:10.1109/test.2014.7035360
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2014 | Conference Paper | LibreCat-ID: 46268
Mohammadi M, Sadeghi-Kohan S, Masoumi N, Navabi Z. An off-line MDSI interconnect BIST incorporated in BS 1149.1. In: 2014 19th IEEE European Test Symposium (ETS). IEEE; 2014. doi:10.1109/ets.2014.6847847
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2014 | Conference Paper | LibreCat-ID: 46267
Sadeghi-Kohan S, Behnam P, Alizadeh B, Fujita M, Navabi Z. Improving polynomial datapath debugging with HEDs. In: 2014 19th IEEE European Test Symposium (ETS). IEEE; 2014. doi:10.1109/ets.2014.6847797
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand S. Analyzing and Quantifying Fault Tolerance Properties. In: 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE; 2013. doi:10.1109/latw.2013.6562662
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2013 | Conference Paper | LibreCat-ID: 46271
Sadeghi-Kohan S, Namaki-Shoushtari M, Javaheri F, Navabi Z. BS 1149.1 extensions for an online interconnect fault detection and recovery. In: 2012 IEEE International Test Conference. IEEE; 2013. doi:10.1109/test.2012.6401583
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2013 | Conference Paper | LibreCat-ID: 46270
Sadeghi-Kohan S, Keshavarz S, Zokaee F, Farahmandi F, Navabi Z. A new structure for interconnect offline testing. In: East-West Design & Test Symposium (EWDTS 2013). IEEE; 2013. doi:10.1109/ewdts.2013.6673207
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2012 | Conference Paper | LibreCat-ID: 12980
Cook A, Hellebrand S, E. Imhof M, Mumtaz A, Wunderlich H-J. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In: 13th IEEE Latin American Test Workshop (LATW’12). Quito, Ecuador: IEEE; 2012:1-4. doi:10.1109/latw.2012.6261229
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2012 | Conference Paper | LibreCat-ID: 12981
Cook A, Hellebrand S, Wunderlich H-J. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In: 17th IEEE European Test Symposium (ETS’12). Annecy, France: IEEE; 2012:1-6. doi:10.1109/ets.2012.6233025
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2011 | Conference Paper | LibreCat-ID: 12982
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Diagnostic Test of Robust Circuits. In: 20th IEEE Asian Test Symposium (ATS’11). New Delhi, India: IEEE; 2011:285-290. doi:10.1109/ats.2011.55
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2011 | Conference Paper | LibreCat-ID: 12984
Polian I, Becker B, Hellebrand S, Wunderlich H-J, Maxwell P. Towards Variation-Aware Test Methods. In: 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE; 2011. doi:10.1109/ets.2011.51
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2011 | Conference Paper | LibreCat-ID: 13053
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Robuster Selbsttest mit Diagnose. In: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf.” Hamburg, Germany; 2011:48-53.
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2011 | Conference Paper | LibreCat-ID: 46272
Kamran A, Nemati N, Sadeghi-Kohan S, Navabi Z. Virtual tester development using HDL/PLI. In: 2010 East-West Design & Test Symposium (EWDTS). IEEE; 2011. doi:10.1109/ewdts.2010.5742156
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2010 | Conference Paper | LibreCat-ID: 12987
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE; 2010. doi:10.1109/dsnw.2010.5542612
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2010 | Conference Paper | LibreCat-ID: 13051
Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19
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2010 | Conference Paper | LibreCat-ID: 12988
Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570
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2010 | Conference Paper | LibreCat-ID: 13049
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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