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84 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, p. 6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, p. 6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023, doi:10.1109/dsn-w58399.2023.00056.
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| DOI
2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023.
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, 2023.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” 38th IEEE VLSI Test Symposium (VTS), IEEE, 2020, doi:10.1109/vts48691.2020.9107591.
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2020 | Conference Paper | LibreCat-ID: 19421
Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE International Test Conference (ITC’20), November 2020, 2020.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
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2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
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| DOI
2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018, doi:10.1109/ddecs.2018.00020.
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2018 | Conference Paper | LibreCat-ID: 10575
Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
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2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017, doi:10.1109/ddecs.2017.7934564.
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2017 | Conference Paper | LibreCat-ID: 29463
Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.” 25th IEEE Asian Test Symposium (ATS’16), IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed Test.” 24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14, doi:10.1109/ats.2015.26.
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| DOI
2015 | Conference Paper | LibreCat-ID: 29465
Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127373.
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| DOI
2015 | Conference Paper | LibreCat-ID: 29466
Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127368.
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| DOI
2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” IEEE International Test Conference (ITC’14), IEEE, 2014, doi:10.1109/test.2014.7035360.
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| DOI
2014 | Conference Paper | LibreCat-ID: 46268
Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847847.
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2014 | Conference Paper | LibreCat-ID: 46267
Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with HEDs.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797.
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand, Sybille. “Analyzing and Quantifying Fault Tolerance Properties.” 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, 2013, doi:10.1109/latw.2013.6562662.
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2013 | Conference Paper | LibreCat-ID: 46271
Sadeghi-Kohan, Somayeh, et al. “BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery.” 2012 IEEE International Test Conference, IEEE, 2013, doi:10.1109/test.2012.6401583.
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2013 | Conference Paper | LibreCat-ID: 46270
Sadeghi-Kohan, Somayeh, et al. “A New Structure for Interconnect Offline Testing.” East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013, doi:10.1109/ewdts.2013.6673207.
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2012 | Conference Paper | LibreCat-ID: 12980
Cook, Alejandro, et al. “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test.” 13th IEEE Latin American Test Workshop (LATW’12), IEEE, 2012, pp. 1–4, doi:10.1109/latw.2012.6261229.
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2012 | Conference Paper | LibreCat-ID: 12981
Cook, Alejandro, et al. “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test.” 17th IEEE European Test Symposium (ETS’12), IEEE, 2012, pp. 1–6, doi:10.1109/ets.2012.6233025.
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2011 | Conference Paper | LibreCat-ID: 12982
Cook, Alejandro, et al. “Diagnostic Test of Robust Circuits.” 20th IEEE Asian Test Symposium (ATS’11), IEEE, 2011, pp. 285–90, doi:10.1109/ats.2011.55.
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| DOI
2011 | Conference Paper | LibreCat-ID: 12984
Polian, Ilia, et al. “Towards Variation-Aware Test Methods.” 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, 2011, doi:10.1109/ets.2011.51.
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| DOI
2011 | Conference Paper | LibreCat-ID: 13053
Cook, Alejandro, et al. “Robuster Selbsttest Mit Diagnose.” 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” 2011, pp. 48–53.
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2011 | Conference Paper | LibreCat-ID: 46272
Kamran, Arezoo, et al. “Virtual Tester Development Using HDL/PLI.” 2010 East-West Design & Test Symposium (EWDTS), IEEE, 2011, doi:10.1109/ewdts.2010.5742156.
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| DOI
2010 | Conference Paper | LibreCat-ID: 12987
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, 2010, doi:10.1109/dsnw.2010.5542612.
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| DOI
2010 | Conference Paper | LibreCat-ID: 13051
Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” 19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” 28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570.
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| DOI
2010 | Conference Paper | LibreCat-ID: 13049
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28.
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30.
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.” 26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34.
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32.
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| DOI
2008 | Conference Paper | LibreCat-ID: 13031
Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
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