Please note that LibreCat no longer supports Internet Explorer versions 8 or 9 (or earlier).
We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.
84 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, p. 6.
LibreCat
2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, p. 6.
LibreCat
2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
LibreCat
2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.
LibreCat
2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023, doi:10.1109/dsn-w58399.2023.00056.
LibreCat
| DOI
2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, 2023.
LibreCat
2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020.
LibreCat
2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” 38th IEEE VLSI Test Symposium (VTS), IEEE, 2020, doi:10.1109/vts48691.2020.9107591.
LibreCat
| DOI
2020 | Conference Paper | LibreCat-ID: 19421
Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE International Test Conference (ITC’20), November 2020, 2020.
LibreCat
2019 | Conference Paper | LibreCat-ID: 12918
Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
LibreCat
2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
LibreCat
| DOI
2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018, doi:10.1109/ddecs.2018.00020.
LibreCat
| DOI
2018 | Conference Paper | LibreCat-ID: 10575
Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
LibreCat
| DOI
2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
LibreCat
| DOI
2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
LibreCat
| DOI
2017 | Conference Paper | LibreCat-ID: 10576
Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017, doi:10.1109/ddecs.2017.7934564.
LibreCat
| DOI
2017 | Conference Paper | LibreCat-ID: 29463
Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
LibreCat
| DOI
2016 | Conference Paper | LibreCat-ID: 12975
Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.” 25th IEEE Asian Test Symposium (ATS’16), IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.
LibreCat
| DOI
2015 | Conference Paper | LibreCat-ID: 12976
Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed Test.” 24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14, doi:10.1109/ats.2015.26.
LibreCat
| DOI
2015 | Conference Paper | LibreCat-ID: 29465
Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127373.
LibreCat
| DOI
2015 | Conference Paper | LibreCat-ID: 29466
Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127368.
LibreCat
| DOI
2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” IEEE International Test Conference (ITC’14), IEEE, 2014, doi:10.1109/test.2014.7035360.
LibreCat
| DOI
2014 | Conference Paper | LibreCat-ID: 46268
Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847847.
LibreCat
| DOI
2014 | Conference Paper | LibreCat-ID: 46267
Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with HEDs.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797.
LibreCat
| DOI
2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand, Sybille. “Analyzing and Quantifying Fault Tolerance Properties.” 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, 2013, doi:10.1109/latw.2013.6562662.
LibreCat
| DOI
2013 | Conference Paper | LibreCat-ID: 46271
Sadeghi-Kohan, Somayeh, et al. “BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery.” 2012 IEEE International Test Conference, IEEE, 2013, doi:10.1109/test.2012.6401583.
LibreCat
| DOI
2013 | Conference Paper | LibreCat-ID: 46270
Sadeghi-Kohan, Somayeh, et al. “A New Structure for Interconnect Offline Testing.” East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013, doi:10.1109/ewdts.2013.6673207.
LibreCat
| DOI
2012 | Conference Paper | LibreCat-ID: 12980
Cook, Alejandro, et al. “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test.” 13th IEEE Latin American Test Workshop (LATW’12), IEEE, 2012, pp. 1–4, doi:10.1109/latw.2012.6261229.
LibreCat
| DOI
2012 | Conference Paper | LibreCat-ID: 12981
Cook, Alejandro, et al. “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test.” 17th IEEE European Test Symposium (ETS’12), IEEE, 2012, pp. 1–6, doi:10.1109/ets.2012.6233025.
LibreCat
| DOI
2011 | Conference Paper | LibreCat-ID: 12982
Cook, Alejandro, et al. “Diagnostic Test of Robust Circuits.” 20th IEEE Asian Test Symposium (ATS’11), IEEE, 2011, pp. 285–90, doi:10.1109/ats.2011.55.
LibreCat
| DOI
2011 | Conference Paper | LibreCat-ID: 12984
Polian, Ilia, et al. “Towards Variation-Aware Test Methods.” 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, 2011, doi:10.1109/ets.2011.51.
LibreCat
| DOI
2011 | Conference Paper | LibreCat-ID: 13053
Cook, Alejandro, et al. “Robuster Selbsttest Mit Diagnose.” 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” 2011, pp. 48–53.
LibreCat
2011 | Conference Paper | LibreCat-ID: 46272
Kamran, Arezoo, et al. “Virtual Tester Development Using HDL/PLI.” 2010 East-West Design & Test Symposium (EWDTS), IEEE, 2011, doi:10.1109/ewdts.2010.5742156.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12987
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, 2010, doi:10.1109/dsnw.2010.5542612.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 13051
Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88.
LibreCat
2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” 19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12986
Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12988
Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” 28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 13049
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24.
LibreCat
2009 | Conference Paper | LibreCat-ID: 12991
Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027.
LibreCat
| DOI
2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28.
LibreCat
| DOI
2009 | Conference Paper | LibreCat-ID: 13030
Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009.
LibreCat
2008 | Conference Paper | LibreCat-ID: 12992
Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30.
LibreCat
| DOI
2008 | Conference Paper | LibreCat-ID: 12994
Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.” 26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34.
LibreCat
| DOI
2008 | Conference Paper | LibreCat-ID: 12993
Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32.
LibreCat
| DOI
2008 | Conference Paper | LibreCat-ID: 13031
Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
LibreCat
2008 | Conference Paper | LibreCat-ID: 13032
Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
LibreCat
2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.” 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, 2007, pp. 50–58, doi:10.1109/dft.2007.43.
LibreCat
| DOI
2007 | Conference Paper | LibreCat-ID: 12996
Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.
LibreCat
| DOI
2007 | Conference Paper | LibreCat-ID: 12997
Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.” 12th IEEE European Test Symposium (ETS’07), IEEE, 2007, pp. 91–96, doi:10.1109/ets.2007.10.
LibreCat
| DOI
2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), 2007.
LibreCat
2007 | Conference Paper | LibreCat-ID: 13040
Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–32.
LibreCat
2007 | Conference Paper | LibreCat-ID: 13041
Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2007.
LibreCat
2005 | Conference Paper | LibreCat-ID: 12999
Ali, Muhammad, et al. “Considerations for Fault-Tolerant Networks on Chips.” IEEE International Conference on Microelectronics (ICM’05), IEEE, 2005, doi:10.1109/icm.2005.1590063.
LibreCat
| DOI
2005 | Conference Paper | LibreCat-ID: 13000
Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.” 10th IEEE European Test Symposium (ETS’05), IEEE, 2005, pp. 148–53, doi:10.1109/ets.2005.28.
LibreCat
| DOI
2005 | Conference Paper | LibreCat-ID: 12998
Ali, Muhammad, et al. “A Dynamic Routing Mechanism for Network on Chip.” 23rd IEEE NORCHIP Conference, IEEE, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991.
LibreCat
| DOI
2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, Michelle, et al. “Sensor Networks with More Features Using Less Hardware.” {GOR/NGB Conference Tilburg 2004}, 2004.
LibreCat
2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger, Armin, et al. “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.” IEEE International Test Conference (ITC’04), IEEE, 2004, pp. 926–35, doi:10.1109/test.2004.1387357.
LibreCat
| DOI
2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger, Armin, et al. “A Hybrid Coding Strategy for Optimized Test Data Compression.” IEEE International Test Conference (ITC’03), IEEE, 2003, pp. 451–59, doi:10.1109/test.2003.1270870.
LibreCat
| DOI
2001 | Conference Paper | LibreCat-ID: 13004
Liang, Hua-Guo, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.” IEEE International Test Conference (ITC’01), IEEE, 2001, pp. 894–902, doi:10.1109/test.2001.966712.
LibreCat
| DOI
2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” IEEE International Test Conference (ITC’00), IEEE, 2000, pp. 778–84, doi:10.1109/test.2000.894274.
LibreCat
| DOI
1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand, Sybille, et al. “Error Detecting Refreshment for Embedded DRAMs.” 17th IEEE VLSI Test Symposium (VTS’99), IEEE, 1999, pp. 384–90, doi:10.1109/vtest.1999.766693.
LibreCat
| DOI
1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik, Vyacheslav, et al. “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.” Third European Dependable Computing Conference (EDCC-3), 1999.
LibreCat
1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand, Sybille, et al. “Symmetric Transparent BIST for RAMs.” Design Automation and Test in Europe (DATE’99), 1999, pp. 702–07.
LibreCat
1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, Andre, et al. “Fast Self-Recovering Controllers.” 16th IEEE VLSI Test Symposium (VTS’98), IEEE, 1998, pp. 296–302, doi:10.1109/vtest.1998.670883.
LibreCat
| DOI
1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, Sybille, et al. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.” Design Automation and Test in Europe (DATE’98), 1998, pp. 173–79, doi:10.1109/date.1998.655853.
LibreCat
| DOI
1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, Vyacheslav, et al. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 1998, pp. 27–33.
LibreCat
1997 | Conference Paper | LibreCat-ID: 13009
Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.” 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.
LibreCat
| DOI
1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.
LibreCat
| DOI
1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.” ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.
LibreCat
| DOI
1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.” ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.
LibreCat
| DOI
1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.” European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.
LibreCat
| DOI
1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman, Srikanth, et al. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.” ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993, doi:10.1109/iccad.1993.580117.
LibreCat
| DOI
1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand, Sybille, et al. “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” IEEE International Test Conference (ITC’92), IEEE, 1992, pp. 120–29, doi:10.1109/test.1992.527812.
LibreCat
| DOI
1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Tools and Devices Supporting the Pseudo-Exhaustive Test.” European Design Automation Conference (EDAC’90), IEEE, 1990, pp. 13–17, doi:10.1109/edac.1990.136612.
LibreCat
| DOI
1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand, Sybille, et al. “Generating Pseudo-Exhaustive Vectors for External Testing.” IEEE International Test Conference (ITC’90), IEEE, 1990, pp. 670–79, doi:10.1109/test.1990.114082.
LibreCat
| DOI
1989 | Conference Paper | LibreCat-ID: 13020
Wunderlich, Hans-Joachim, and Sybille Hellebrand. “The Pseudo-Exhaustive Test of Sequential Circuits.” IEEE International Test Conference (ITC’89), IEEE, 1989, pp. 19–27, doi:10.1109/test.1989.82273.
LibreCat
| DOI
1988 | Conference Paper | LibreCat-ID: 13021
Wunderlich, Hans-Joachim, and Sybille Hellebrand. “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits.” 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi:10.1109/ftcs.1988.5294.
LibreCat
| DOI
1988 | Conference Paper | LibreCat-ID: 13058
Schmid, Detlef, et al. “Integrated Tools for Automatic Design for Testability.” Tool Integration and Design Environments, F.J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, 1988, pp. 233–58.
LibreCat
1988 | Conference Paper | LibreCat-ID: 13062
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Automatisierung Des Entwurfs Vollständig Testbarer Schaltungen.” GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, Springer Verlag, 1988, pp. 145–59.
LibreCat