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165 Publications
2012 | Misc | LibreCat-ID: 13074
A. Cook, S. Hellebrand, and H.-J. Wunderlich, Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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2011 | Conference Paper | LibreCat-ID: 13053
A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
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2011 | Journal Article | LibreCat-ID: 13052
F. Hopsch et al., “Variation-Aware Fault Modeling,” SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, vol. 54, no. 4, pp. 1813–1826, 2011.
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2011 | Conference Paper | LibreCat-ID: 46272
A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,” 2011, doi: 10.1109/ewdts.2010.5742156.
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2010 | Misc | LibreCat-ID: 10670
V. Fröse, R. Ibers, and S. Hellebrand, Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
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2010 | Misc | LibreCat-ID: 13073
S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010.
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2010 | Conference Paper | LibreCat-ID: 12983
F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.
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2010 | Conference Paper | LibreCat-ID: 13049
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.
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2009 | Conference Paper | LibreCat-ID: 13030
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
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2008 | Misc | LibreCat-ID: 13033
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
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2008 | Misc | LibreCat-ID: 13035
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,” 2008, doi: 10.1109/iolts.2008.30.
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2008 | Conference Paper | LibreCat-ID: 12994
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,” in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi: 10.1109/vts.2008.34.
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2008 | Conference Paper | LibreCat-ID: 12993
M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,” 2008, doi: 10.1109/iolts.2008.32.
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2008 | Conference Paper | LibreCat-ID: 13031
M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.
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2007 | Misc | LibreCat-ID: 13038
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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2007 | Misc | LibreCat-ID: 13039
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
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2007 | Misc | LibreCat-ID: 13042
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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2007 | Misc | LibreCat-ID: 13043
S. Hellebrand, Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,” in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi: 10.1109/dft.2007.43.
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2007 | Conference Paper | LibreCat-ID: 12996
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi: 10.1109/ddecs.2007.4295278.
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2007 | Conference Paper | LibreCat-ID: 12997
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi: 10.1109/ets.2007.10.
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2007 | Conference Paper | LibreCat-ID: 13037
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
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2007 | Journal Article | LibreCat-ID: 13036
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), pp. 212–219, 2007.
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2007 | Journal Article | LibreCat-ID: 13044
M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” International Journal on High Performance Systems Architecture, vol. 1, no. 2, pp. 113–123, 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
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2006 | Journal Article | LibreCat-ID: 13045
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” it - Information Technology, vol. 48, no. 5, pp. 305–311, 2006.
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2005 | Misc | LibreCat-ID: 13046
P. Oehler and S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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2005 | Misc | LibreCat-ID: 13101
M. Ali, M. Welzl, and S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Misc | LibreCat-ID: 13102
P. Oehler and S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,” 2005, doi: 10.1109/icm.2005.1590063.
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2005 | Conference Paper | LibreCat-ID: 13000
P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,” in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi: 10.1109/ets.2005.28.
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2005 | Conference Paper | LibreCat-ID: 12998
M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,” in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi: 10.1109/norchp.2005.1596991.
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2004 | Conference Paper | LibreCat-ID: 13071
M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in {GOR/NGB Conference Tilburg 2004}, 2004.
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2004 | Misc | LibreCat-ID: 13099
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, and O. Scherzer, Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29, 2004.
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2004 | Misc | LibreCat-ID: 13100
S. Hellebrand, A. Wuertenberger, and C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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