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165 Publications
2007 | Misc | LibreCat-ID: 13042
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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2007 | Misc | LibreCat-ID: 13043
S. Hellebrand, Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,” in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi: 10.1109/dft.2007.43.
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2007 | Conference Paper | LibreCat-ID: 12996
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi: 10.1109/ddecs.2007.4295278.
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2007 | Conference Paper | LibreCat-ID: 12997
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi: 10.1109/ets.2007.10.
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2007 | Conference Paper | LibreCat-ID: 13037
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
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2007 | Journal Article | LibreCat-ID: 13036
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), pp. 212–219, 2007.
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2007 | Journal Article | LibreCat-ID: 13044
M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” International Journal on High Performance Systems Architecture, vol. 1, no. 2, pp. 113–123, 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
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2006 | Journal Article | LibreCat-ID: 13045
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” it - Information Technology, vol. 48, no. 5, pp. 305–311, 2006.
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2005 | Misc | LibreCat-ID: 13046
P. Oehler and S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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2005 | Misc | LibreCat-ID: 13101
M. Ali, M. Welzl, and S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Misc | LibreCat-ID: 13102
P. Oehler and S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,” 2005, doi: 10.1109/icm.2005.1590063.
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2005 | Conference Paper | LibreCat-ID: 13000
P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,” in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi: 10.1109/ets.2005.28.
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2005 | Conference Paper | LibreCat-ID: 12998
M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,” in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi: 10.1109/norchp.2005.1596991.
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2004 | Conference Paper | LibreCat-ID: 13071
M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in {GOR/NGB Conference Tilburg 2004}, 2004.
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2004 | Misc | LibreCat-ID: 13099
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, and O. Scherzer, Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29, 2004.
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2004 | Misc | LibreCat-ID: 13100
S. Hellebrand, A. Wuertenberger, and C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections,” in IEEE International Test Conference (ITC’04), 2004, pp. 926–935, doi: 10.1109/test.2004.1387357.
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2003 | Misc | LibreCat-ID: 13098
R. Breu, S. Hellebrand, and M. Welzl, Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
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2003 | Conference Paper | LibreCat-ID: 13002
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “A Hybrid Coding Strategy for Optimized Test Data Compression,” in IEEE International Test Conference (ITC’03), 2003, pp. 451–459, doi: 10.1109/test.2003.1270870.
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2002 | Misc | LibreCat-ID: 13097
S. Hellebrand and A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
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2002 | Journal Article | LibreCat-ID: 13003
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Efficient Online and Offline Testing of Embedded DRAMs,” IEEE Transactions on Computers, vol. 51, no. 7, pp. 801–809, 2002, doi: 10.1109/tc.2002.1017700.
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2002 | Journal Article | LibreCat-ID: 13069
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, pp. 157–168, 2002.
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2002 | Journal Article | LibreCat-ID: 13070
H. Liang, S. Hellebrand, and H.-J. Wunderlich, “A Mixed-Mode BIST Scheme Based on Folding Compression,” Journal on Computer Science and Technology, vol. 17, no. 2, pp. 203–212, 2002.
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2001 | Misc | LibreCat-ID: 13096
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden, 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” in IEEE International Test Conference (ITC’01), 2001, pp. 894–902, doi: 10.1109/test.2001.966712.
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2001 | Journal Article | LibreCat-ID: 13047
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Deterministic BIST Scheme Based on Reseeding of Folding Counters,” Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan), vol. 38, no. 8, p. 931, 2001.
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2001 | Journal Article | LibreCat-ID: 13068
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, pp. 341–349, 2001.
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2000 | Misc | LibreCat-ID: 13094
S. Hellebrand and H.-J. Wunderlich, Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag, 2000.
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2000 | Misc | LibreCat-ID: 13095
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal, 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” in IEEE International Test Conference (ITC’00), 2000, pp. 778–784, doi: 10.1109/test.2000.894274.
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1999 | Book | LibreCat-ID: 13065
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg, 1999.
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1999 | Misc | LibreCat-ID: 13093
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop, 1999.
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1999 | Conference Paper | LibreCat-ID: 13006
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Error Detecting Refreshment for Embedded DRAMs,” in 17th IEEE VLSI Test Symposium (VTS’99), 1999, pp. 384–390, doi: 10.1109/vtest.1999.766693.
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1999 | Conference Paper | LibreCat-ID: 13066
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms,” 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Symmetric Transparent BIST for RAMs,” in Design Automation and Test in Europe (DATE’99), 1999, pp. 702–707.
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1998 | Report | LibreCat-ID: 13029
S. Hellebrand and H.-J. Wunderlich, Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart, 1998.
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1998 | Misc | LibreCat-ID: 13091
V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
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1998 | Misc | LibreCat-ID: 13092
V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.
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1998 | Book Chapter | LibreCat-ID: 13060
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in Mixed-Mode BIST Using Embedded Processors, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.
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1998 | Journal Article | LibreCat-ID: 13061
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, pp. 127–138, 1998.
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1998 | Journal Article | LibreCat-ID: 13064
S. Hellebrand, A. Hertwig, and H.-J. Wunderlich, “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications,” IEEE Design and Test, vol. 15, no. 4, pp. 36–41, 1998.
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1998 | Conference Paper | LibreCat-ID: 13007
A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,” in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi: 10.1109/vtest.1998.670883.
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1998 | Conference Paper | LibreCat-ID: 13008
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,” in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi: 10.1109/date.1998.655853.
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1998 | Conference Paper | LibreCat-ID: 13063
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 1998, pp. 27–33.
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1997 | Misc | LibreCat-ID: 13089
K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
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1997 | Misc | LibreCat-ID: 13090
A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,” 1997, doi: 10.1109/dac.1997.597194.
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1996 | Misc | LibreCat-ID: 13087
S. Hellebrand and H.-J. Wunderlich, Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
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1996 | Misc | LibreCat-ID: 13088
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi: 10.1109/test.1996.556962.
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1995 | Report | LibreCat-ID: 13026
S. Hellebrand and H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13027
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, and J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13028
S. Hellebrand, M. Herzog, and H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
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1995 | Misc | LibreCat-ID: 13086
S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
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1995 | Journal Article | LibreCat-ID: 13011
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Transactions on Computers, vol. 44, no. 2, pp. 223–233, 1995, doi: 10.1109/12.364534.
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1995 | Conference Paper | LibreCat-ID: 13012
S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,” in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi: 10.1109/iccad.1995.479997.
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1994 | Report | LibreCat-ID: 13024
S. Hellebrand, A. Juergensen, and H.-J. Wunderlich, Synthesis for Off-line Testability. University of Siegen, Germany, 1994.
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1994 | Report | LibreCat-ID: 13025
S. Hellebrand, A. Juergensen, A. Stroele, and H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany, 1994.
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1994 | Misc | LibreCat-ID: 13083
S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
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1994 | Misc | LibreCat-ID: 13084
S. Hellebrand and H.-J. Wunderlich, Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
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1994 | Misc | LibreCat-ID: 13085
S. Hellebrand, J. Paulo Teixeira, and H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,” in ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 1994, pp. 110–116, doi: 10.1109/iccad.1994.629752.
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1994 | Conference Paper | LibreCat-ID: 13059
S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in Tagungsband der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,” in European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–585, doi: 10.1109/edtc.1994.326815.
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1993 | Misc | LibreCat-ID: 13081
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
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1993 | Misc | LibreCat-ID: 13082
S. Hellebrand and H.-J. Wunderlich, Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,” 1993, doi: 10.1109/iccad.1993.580117.
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1992 | Report | LibreCat-ID: 13023
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
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1992 | Misc | LibreCat-ID: 13076
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
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1992 | Misc | LibreCat-ID: 13080
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada, 1992.
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1992 | Journal Article | LibreCat-ID: 13017
H.-J. Wunderlich and S. Hellebrand, “The Pseudoexhaustive Test of Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, pp. 26–33, 1992, doi: 10.1109/43.108616.
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1992 | Conference Paper | LibreCat-ID: 13016
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” in IEEE International Test Conference (ITC’92), 1992, pp. 120–129, doi: 10.1109/test.1992.527812.
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1991 | Book | LibreCat-ID: 13034
S. Hellebrand, Synthese vollständig testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag, 1991.
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1990 | Misc | LibreCat-ID: 13103
S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
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1990 | Conference Paper | LibreCat-ID: 13018
S. Hellebrand and H.-J. Wunderlich, “Tools and Devices Supporting the Pseudo-Exhaustive Test,” in European Design Automation Conference (EDAC’90), 1990, pp. 13–17, doi: 10.1109/edac.1990.136612.
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1990 | Conference Paper | LibreCat-ID: 13019
S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,” in IEEE International Test Conference (ITC’90), 1990, pp. 670–679, doi: 10.1109/test.1990.114082.
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1989 | Conference Paper | LibreCat-ID: 13020
H.-J. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,” in IEEE International Test Conference (ITC’89), 1989, pp. 19–27, doi: 10.1109/test.1989.82273.
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1988 | Conference Paper | LibreCat-ID: 13021
H.-J. Wunderlich and S. Hellebrand, “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits,” in 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi: 10.1109/ftcs.1988.5294.
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1988 | Conference Paper | LibreCat-ID: 13058
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, and A. Kunzmann, “Integrated Tools for Automatic Design for Testability,” in Tool Integration and Design Environments, F.J. Rammig (Editor), 1988, pp. 233–258.
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1988 | Conference Paper | LibreCat-ID: 13062
S. Hellebrand and H.-J. Wunderlich, “Automatisierung des Entwurfs vollständig testbarer Schaltungen,” in GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 1988, pp. 145–159.
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1986 | Report | LibreCat-ID: 13022
S. Hellebrand, Deformation dicker Punkte und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
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