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165 Publications
2010 | Conference Paper | LibreCat-ID: 13051
Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” 19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” 28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570.
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2010 | Conference Paper | LibreCat-ID: 13049
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28.
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009.
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2008 | Misc | LibreCat-ID: 13033
Coym, Torsten, et al. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 2008.
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2008 | Misc | LibreCat-ID: 13035
Amgalan, Uranmandakh, et al. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30.
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.” 26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34.
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32.
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.
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2007 | Misc | LibreCat-ID: 13038
Hellebrand, Sybille. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 2007.
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2007 | Misc | LibreCat-ID: 13039
Ali, Muhammad, et al. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. 2007.
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2007 | Misc | LibreCat-ID: 13042
Oehler, Philipp, et al. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 2007.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand, Sybille. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.” 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, 2007, pp. 50–58, doi:10.1109/dft.2007.43.
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.” 12th IEEE European Test Symposium (ETS’07), IEEE, 2007, pp. 91–96, doi:10.1109/ets.2007.10.
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), 2007.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), 2007, pp. 212–19.
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2007 | Journal Article | LibreCat-ID: 13044
Ali, Muhammad, et al. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” International Journal on High Performance Systems Architecture, vol. 1, no. 2, 2007, pp. 113–23.
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2007 | Conference Paper | LibreCat-ID: 13040
Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–32.
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2007 | Conference Paper | LibreCat-ID: 13041
Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2007.
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2006 | Journal Article | LibreCat-ID: 13045
Becker, Bernd, et al. “DFG-Projekt RealTest - Test Und Zuverlässigkeit Nanoelektronischer Systeme.” It - Information Technology, vol. 48, no. 5, 2006, pp. 305–11.
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2005 | Misc | LibreCat-ID: 13046
Oehler, Philipp, and Sybille Hellebrand. A Low Power Design for Embedded DRAMs with Online Consistency Checking. 2005.
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2005 | Misc | LibreCat-ID: 13101
Ali, Muhammad, et al. Dynamic Routing: A Prerequisite for Reliable NoCs. 2005.
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2005 | Misc | LibreCat-ID: 13102
Oehler, Philipp, and Sybille Hellebrand. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
Ali, Muhammad, et al. “Considerations for Fault-Tolerant Networks on Chips.” IEEE International Conference on Microelectronics (ICM’05), IEEE, 2005, doi:10.1109/icm.2005.1590063.
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.” 10th IEEE European Test Symposium (ETS’05), IEEE, 2005, pp. 148–53, doi:10.1109/ets.2005.28.
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, Muhammad, et al. “A Dynamic Routing Mechanism for Network on Chip.” 23rd IEEE NORCHIP Conference, IEEE, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991.
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, Michelle, et al. “Sensor Networks with More Features Using Less Hardware.” {GOR/NGB Conference Tilburg 2004}, 2004.
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2004 | Misc | LibreCat-ID: 13099
Breu, Ruth, et al. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. 2004.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand, Sybille, et al. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger, Armin, et al. “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.” IEEE International Test Conference (ITC’04), IEEE, 2004, pp. 926–35, doi:10.1109/test.2004.1387357.
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2003 | Misc | LibreCat-ID: 13098
Breu, Ruth, et al. Experiences from Teaching Software Development in a Java Environment. 2003.
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger, Armin, et al. “A Hybrid Coding Strategy for Optimized Test Data Compression.” IEEE International Test Conference (ITC’03), IEEE, 2003, pp. 451–59, doi:10.1109/test.2003.1270870.
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2002 | Misc | LibreCat-ID: 13097
Hellebrand, Sybille, and Armin Wuertenberger. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. 2002.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand, Sybille, et al. “Efficient Online and Offline Testing of Embedded DRAMs.” IEEE Transactions on Computers, vol. 51, no. 7, IEEE, 2002, pp. 801–09, doi:10.1109/tc.2002.1017700.
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand, Sybille, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, 2002, pp. 157–68.
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2002 | Journal Article | LibreCat-ID: 13070
Liang, Huaguo, et al. “A Mixed-Mode BIST Scheme Based on Folding Compression.” Journal on Computer Science and Technology, vol. 17, no. 2, 2002, pp. 203–12.
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2001 | Misc | LibreCat-ID: 13096
Liang, Hua-Guo, et al. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
Liang, Hua-Guo, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.” IEEE International Test Conference (ITC’01), IEEE, 2001, pp. 894–902, doi:10.1109/test.2001.966712.
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2001 | Journal Article | LibreCat-ID: 13047
Liang, Hua-Guo, et al. “Deterministic BIST Scheme Based on Reseeding of Folding Counters.” Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), vol. 38, no. 8, 2001, p. 931.
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2001 | Journal Article | LibreCat-ID: 13068
Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, 2001, pp. 341–49.
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2000 | Misc | LibreCat-ID: 13094
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Hardwarepraktikum Im Diplomstudiengang Informatik. 2000.
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2000 | Misc | LibreCat-ID: 13095
Hellebrand, Sybille, et al. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” IEEE International Test Conference (ITC’00), IEEE, 2000, pp. 778–84, doi:10.1109/test.2000.894274.
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1999 | Book | LibreCat-ID: 13065
Hellebrand, Sybille. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg, 1999.
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1999 | Misc | LibreCat-ID: 13093
Hellebrand, Sybille, et al. Exploiting Symmetries to Speed Up Transparent BIST. 1999.
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand, Sybille, et al. “Error Detecting Refreshment for Embedded DRAMs.” 17th IEEE VLSI Test Symposium (VTS’99), IEEE, 1999, pp. 384–90, doi:10.1109/vtest.1999.766693.
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1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik, Vyacheslav, et al. “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.” Third European Dependable Computing Conference (EDCC-3), 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand, Sybille, et al. “Symmetric Transparent BIST for RAMs.” Design Automation and Test in Europe (DATE’99), 1999, pp. 702–07.
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1998 | Report | LibreCat-ID: 13029
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Test Und Synthese Schneller Eingebetteter Systeme. 1998.
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1998 | Misc | LibreCat-ID: 13091
N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
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1998 | Misc | LibreCat-ID: 13092
N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
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1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, 1998.
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1998 | Journal Article | LibreCat-ID: 13061
Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, 1998, pp. 127–38.
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1998 | Journal Article | LibreCat-ID: 13064
Hellebrand, Sybille, et al. “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications.” IEEE Design and Test, vol. 15, no. 4, IEEE, 1998, pp. 36–41.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, Andre, et al. “Fast Self-Recovering Controllers.” 16th IEEE VLSI Test Symposium (VTS’98), IEEE, 1998, pp. 296–302, doi:10.1109/vtest.1998.670883.
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, Sybille, et al. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.” Design Automation and Test in Europe (DATE’98), 1998, pp. 173–79, doi:10.1109/date.1998.655853.
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, Vyacheslav, et al. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 1998, pp. 27–33.
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1997 | Misc | LibreCat-ID: 13089
Tsai, Kun-Han, et al. STARBIST: Scan Autocorrelated Random Pattern Generation. 1997.
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1997 | Misc | LibreCat-ID: 13090
Hertwig, Andre, et al. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.” 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 1996.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand, Sybille, et al. Mixed-Mode BIST Using Embedded Processors. 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.
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1995 | Report | LibreCat-ID: 13026
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. 1995.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, Sybille, et al. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. 1995.
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1995 | Report | LibreCat-ID: 13028
Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.
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1995 | Misc | LibreCat-ID: 13086
Hellebrand, Sybille, et al. Pattern Generation for a Deterministic BIST Scheme. 1995.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” IEEE Transactions on Computers, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:10.1109/12.364534.
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.” ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.
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1994 | Report | LibreCat-ID: 13024
Hellebrand, Sybille, et al. Synthesis for Off-Line Testability. 1994.
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1994 | Report | LibreCat-ID: 13025
Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.
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1994 | Misc | LibreCat-ID: 13083
Venkataraman, Srikanth, et al. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 1994.
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1994 | Misc | LibreCat-ID: 13084
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 1994.
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1994 | Misc | LibreCat-ID: 13085
Hellebrand, Sybille, et al. Synthesis for Testability - the ARCHIMEDES Approach. 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.” ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.” European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.
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1993 | Misc | LibreCat-ID: 13081
Hellebrand, Sybille, et al. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 1993.
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1993 | Misc | LibreCat-ID: 13082
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis of Self-Testable Controllers. 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman, Srikanth, et al. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.” ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993, doi:10.1109/iccad.1993.580117.
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1992 | Report | LibreCat-ID: 13023
Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
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1992 | Misc | LibreCat-ID: 13076
Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
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1992 | Misc | LibreCat-ID: 13080
Hellebrand, Sybille, et al. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. 1992.
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1992 | Journal Article | LibreCat-ID: 13017
Wunderlich, Hans-Joachim, and Sybille Hellebrand. “The Pseudoexhaustive Test of Sequential Circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, Institute of Electrical and Electronics Engineers (IEEE), 1992, pp. 26–33, doi:10.1109/43.108616.
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1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand, Sybille, et al. “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” IEEE International Test Conference (ITC’92), IEEE, 1992, pp. 120–29, doi:10.1109/test.1992.527812.
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1991 | Book | LibreCat-ID: 13034
Hellebrand, Sybille. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag, 1991.
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1990 | Misc | LibreCat-ID: 13103
Hellebrand, Sybille, et al. Generating Pseudo-Exhaustive Vectors for External Testing. 1990.
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1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Tools and Devices Supporting the Pseudo-Exhaustive Test.” European Design Automation Conference (EDAC’90), IEEE, 1990, pp. 13–17, doi:10.1109/edac.1990.136612.
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1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand, Sybille, et al. “Generating Pseudo-Exhaustive Vectors for External Testing.” IEEE International Test Conference (ITC’90), IEEE, 1990, pp. 670–79, doi:10.1109/test.1990.114082.
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