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84 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich, H.-J., Jafarzadeh, H., & Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056
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2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS). https://doi.org/10.1109/vts48691.2020.9107591
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2020 | Conference Paper | LibreCat-ID: 19421
Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
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2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI. https://doi.org/10.1145/3194554.3194599
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
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2018 | Conference Paper | LibreCat-ID: 10575
Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028
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2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). https://doi.org/10.1109/ddecs.2017.7934564
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2017 | Conference Paper | LibreCat-ID: 29463
Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann, M., & Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE. https://doi.org/10.1109/ats.2016.20
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE. https://doi.org/10.1109/ats.2015.26
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2015 | Conference Paper | LibreCat-ID: 29465
Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., & Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127373
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2015 | Conference Paper | LibreCat-ID: 29466
Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., & Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127368
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2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., & Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE. https://doi.org/10.1109/test.2014.7035360
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2014 | Conference Paper | LibreCat-ID: 46268
Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., & Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847847
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2014 | Conference Paper | LibreCat-ID: 46267
Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., & Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847797
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE. https://doi.org/10.1109/latw.2013.6562662
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2013 | Conference Paper | LibreCat-ID: 46271
Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., & Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference. https://doi.org/10.1109/test.2012.6401583
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2013 | Conference Paper | LibreCat-ID: 46270
Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., & Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design & Test Symposium (EWDTS 2013). https://doi.org/10.1109/ewdts.2013.6673207
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2012 | Conference Paper | LibreCat-ID: 12980
Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., & Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE. https://doi.org/10.1109/latw.2012.6261229
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2012 | Conference Paper | LibreCat-ID: 12981
Cook, A., Hellebrand, S., & Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE. https://doi.org/10.1109/ets.2012.6233025
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2011 | Conference Paper | LibreCat-ID: 12982
Cook, A., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE. https://doi.org/10.1109/ats.2011.55
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2011 | Conference Paper | LibreCat-ID: 12984
Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., & Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE. https://doi.org/10.1109/ets.2011.51
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2011 | Conference Paper | LibreCat-ID: 13053
Cook, A., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.
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2011 | Conference Paper | LibreCat-ID: 46272
Kamran, A., Nemati, N., Sadeghi-Kohan, S., & Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2010.5742156
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2010 | Conference Paper | LibreCat-ID: 12987
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE. https://doi.org/10.1109/dsnw.2010.5542612
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2010 | Conference Paper | LibreCat-ID: 13051
Hunger, M., & Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93. https://doi.org/10.1109/ats.2010.24
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485. https://doi.org/10.1109/iccd.2010.5647648
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger, M., & Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108. https://doi.org/10.1109/dft.2010.19
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2010 | Conference Paper | LibreCat-ID: 12988
Froese, V., Ibers, R., & Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231. https://doi.org/10.1109/vts.2010.5469570
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2010 | Conference Paper | LibreCat-ID: 13049
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09. https://doi.org/10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, S., & Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. https://doi.org/10.1109/dft.2009.28
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler, P., Bosio, A., di Natale, G., & Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). https://doi.org/10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan, U., Hachmann, C., Hellebrand, S., & Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130. https://doi.org/10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger, M., & Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08). https://doi.org/10.1109/iolts.2008.32
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger, M., & Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler, P., Bosio, A., Di Natale, G., & Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58. https://doi.org/10.1109/dft.2007.43
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190. https://doi.org/10.1109/ddecs.2007.4295278
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96. https://doi.org/10.1109/ets.2007.10
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).
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2007 | Conference Paper | LibreCat-ID: 13040
Ali, M., Welzl, M., Hessler, S., & Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
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2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05). https://doi.org/10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153. https://doi.org/10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73. https://doi.org/10.1109/norchp.2005.1596991
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A., … Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In {GOR/NGB Conference Tilburg 2004}. Tilburg, Netherlands.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. IEEE International Test Conference (ITC’04), 926–935. https://doi.org/10.1109/test.2004.1387357
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2003). A Hybrid Coding Strategy for Optimized Test Data Compression. IEEE International Test Conference (ITC’03), 451–459. https://doi.org/10.1109/test.2003.1270870
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2001 | Conference Paper | LibreCat-ID: 13004
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE International Test Conference (ITC’01), 894–902. https://doi.org/10.1109/test.2001.966712
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE International Test Conference (ITC’00), 778–784. https://doi.org/10.1109/test.2000.894274
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., & N. Yarmolik, V. (1999). Error Detecting Refreshment for Embedded DRAMs. 17th IEEE VLSI Test Symposium (VTS’99), 384–390. https://doi.org/10.1109/vtest.1999.766693
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1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik, V., V. Bykov, I., Hellebrand, S., & Wunderlich, H.-J. (1999). Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. Third European Dependable Computing Conference (EDCC-3).
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1999). Symmetric Transparent BIST for RAMs. Design Automation and Test in Europe (DATE’99), 702–707.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, A., Hellebrand, S., & Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. 16th IEEE VLSI Test Symposium (VTS’98), 296–302. https://doi.org/10.1109/vtest.1998.670883
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Design Automation and Test in Europe (DATE’98), 173–179. https://doi.org/10.1109/date.1998.655853
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., & Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 27–33.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., & Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97). https://doi.org/10.1109/dac.1997.597194
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204. https://doi.org/10.1109/test.1996.556962
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94. https://doi.org/10.1109/iccad.1995.479997
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, S., & Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116. https://doi.org/10.1109/iccad.1994.629752
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585. https://doi.org/10.1109/edtc.1994.326815
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). https://doi.org/10.1109/iccad.1993.580117
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1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE International Test Conference (ITC’92), 120–129. https://doi.org/10.1109/test.1992.527812
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1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand, S., & Wunderlich, H.-J. (1990). Tools and Devices Supporting the Pseudo-Exhaustive Test. European Design Automation Conference (EDAC’90), 13–17. https://doi.org/10.1109/edac.1990.136612
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| DOI
1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand, S., Wunderlich, H.-J., & F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE International Test Conference (ITC’90), 670–679. https://doi.org/10.1109/test.1990.114082
LibreCat
| DOI
1989 | Conference Paper | LibreCat-ID: 13020
Wunderlich, H.-J., & Hellebrand, S. (1989). The Pseudo-Exhaustive Test of Sequential Circuits. IEEE International Test Conference (ITC’89), 19–27. https://doi.org/10.1109/test.1989.82273
LibreCat
| DOI
1988 | Conference Paper | LibreCat-ID: 13021
Wunderlich, H.-J., & Hellebrand, S. (1988). Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 36–45. https://doi.org/10.1109/ftcs.1988.5294
LibreCat
| DOI
1988 | Conference Paper | LibreCat-ID: 13058
Schmid, D., Wunderlich, H.-J., Feldbusch, F., Hellebrand, S., Holzinger, J., & Kunzmann, A. (1988). Integrated Tools for Automatic Design for Testability. Tool Integration and Design Environments, F.J. Rammig (Editor), 233–258.
LibreCat
1988 | Conference Paper | LibreCat-ID: 13062
Hellebrand, S., & Wunderlich, H.-J. (1988). Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 145–159.
LibreCat