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84 Publications
2024 | Conference Paper | LibreCat-ID: 52744
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations,” in European Test Symposium, The Hague, Netherlands, May 20-24, 2024, The Hague, NL, p. 6.
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2024 | Conference Paper | LibreCat-ID: 52742
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Vmin Testing under Variations: Defect vs. Fault Coverage,” in IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, Maceió, p. 6.
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2024 | Conference Paper | LibreCat-ID: 52743
S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1.
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2024 | Conference Paper | LibreCat-ID: 52745
H.-J. Wunderlich, H. Jafarzadeh, and S. Hellebrand, “Robust Test of Small Delay Faults under PVT-Variations,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1.
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2023 | Conference Paper | LibreCat-ID: 46739
S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: 10.1109/dsn-w58399.2023.00056.
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2023 | Conference Paper | LibreCat-ID: 46738
S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.
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2023 | Conference Paper | LibreCat-ID: 45830
H. Jafarzadeh et al., “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023.
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2020 | Conference Paper | LibreCat-ID: 19422
A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: 10.1109/vts48691.2020.9107591.
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2020 | Conference Paper | LibreCat-ID: 19421
S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.
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2019 | Conference Paper | LibreCat-ID: 12918
M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC), Washington, DC, USA, 2019, pp. 1–8.
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2018 | Conference Paper | LibreCat-ID: 29460
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: 10.1145/3194554.3194599.
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2018 | Conference Paper | LibreCat-ID: 4575
A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: 10.1109/ddecs.2018.00020.
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2018 | Conference Paper | LibreCat-ID: 10575
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.
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2018 | Conference Paper | LibreCat-ID: 29459
S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.
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2017 | Conference Paper | LibreCat-ID: 10576
M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.
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2017 | Conference Paper | LibreCat-ID: 29463
M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.
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2015 | Conference Paper | LibreCat-ID: 29465
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: 10.1109/dtis.2015.7127373.
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2015 | Conference Paper | LibreCat-ID: 29466
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.
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2014 | Conference Paper | LibreCat-ID: 46268
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.
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2014 | Conference Paper | LibreCat-ID: 46267
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.
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2013 | Conference Paper | LibreCat-ID: 46271
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, and Z. Navabi, “BS 1149.1 extensions for an online interconnect fault detection and recovery,” 2013, doi: 10.1109/test.2012.6401583.
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2013 | Conference Paper | LibreCat-ID: 46270
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, and Z. Navabi, “A new structure for interconnect offline testing,” 2013, doi: 10.1109/ewdts.2013.6673207.
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2011 | Conference Paper | LibreCat-ID: 13053
A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
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2011 | Conference Paper | LibreCat-ID: 46272
A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,” 2011, doi: 10.1109/ewdts.2010.5742156.
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2010 | Conference Paper | LibreCat-ID: 12987
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
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2010 | Conference Paper | LibreCat-ID: 12983
F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.
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2010 | Conference Paper | LibreCat-ID: 13049
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.
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2009 | Conference Paper | LibreCat-ID: 13030
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
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2008 | Conference Paper | LibreCat-ID: 12992
P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,” 2008, doi: 10.1109/iolts.2008.30.
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2008 | Conference Paper | LibreCat-ID: 12994
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,” in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi: 10.1109/vts.2008.34.
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2008 | Conference Paper | LibreCat-ID: 12993
M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,” 2008, doi: 10.1109/iolts.2008.32.
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2008 | Conference Paper | LibreCat-ID: 13031
M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.
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2007 | Conference Paper | LibreCat-ID: 12995
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,” in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi: 10.1109/dft.2007.43.
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2007 | Conference Paper | LibreCat-ID: 12996
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi: 10.1109/ddecs.2007.4295278.
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2007 | Conference Paper | LibreCat-ID: 12997
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi: 10.1109/ets.2007.10.
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2007 | Conference Paper | LibreCat-ID: 13037
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
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2005 | Conference Paper | LibreCat-ID: 12999
M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,” 2005, doi: 10.1109/icm.2005.1590063.
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2005 | Conference Paper | LibreCat-ID: 13000
P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,” in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi: 10.1109/ets.2005.28.
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2005 | Conference Paper | LibreCat-ID: 12998
M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,” in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi: 10.1109/norchp.2005.1596991.
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2004 | Conference Paper | LibreCat-ID: 13071
M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in {GOR/NGB Conference Tilburg 2004}, 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections,” in IEEE International Test Conference (ITC’04), 2004, pp. 926–935, doi: 10.1109/test.2004.1387357.
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2003 | Conference Paper | LibreCat-ID: 13002
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “A Hybrid Coding Strategy for Optimized Test Data Compression,” in IEEE International Test Conference (ITC’03), 2003, pp. 451–459, doi: 10.1109/test.2003.1270870.
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2001 | Conference Paper | LibreCat-ID: 13004
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” in IEEE International Test Conference (ITC’01), 2001, pp. 894–902, doi: 10.1109/test.2001.966712.
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2000 | Conference Paper | LibreCat-ID: 13005
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” in IEEE International Test Conference (ITC’00), 2000, pp. 778–784, doi: 10.1109/test.2000.894274.
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1999 | Conference Paper | LibreCat-ID: 13006
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Error Detecting Refreshment for Embedded DRAMs,” in 17th IEEE VLSI Test Symposium (VTS’99), 1999, pp. 384–390, doi: 10.1109/vtest.1999.766693.
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1999 | Conference Paper | LibreCat-ID: 13066
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms,” 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Symmetric Transparent BIST for RAMs,” in Design Automation and Test in Europe (DATE’99), 1999, pp. 702–707.
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1998 | Conference Paper | LibreCat-ID: 13007
A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,” in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi: 10.1109/vtest.1998.670883.
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1998 | Conference Paper | LibreCat-ID: 13008
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,” in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi: 10.1109/date.1998.655853.
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1998 | Conference Paper | LibreCat-ID: 13063
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 1998, pp. 27–33.
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1997 | Conference Paper | LibreCat-ID: 13009
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,” 1997, doi: 10.1109/dac.1997.597194.
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1996 | Conference Paper | LibreCat-ID: 13010
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi: 10.1109/test.1996.556962.
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1995 | Conference Paper | LibreCat-ID: 13012
S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,” in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi: 10.1109/iccad.1995.479997.
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1994 | Conference Paper | LibreCat-ID: 13014
S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,” in ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 1994, pp. 110–116, doi: 10.1109/iccad.1994.629752.
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1994 | Conference Paper | LibreCat-ID: 13059
S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in Tagungsband der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,” in European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–585, doi: 10.1109/edtc.1994.326815.
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1993 | Conference Paper | LibreCat-ID: 13015
S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,” 1993, doi: 10.1109/iccad.1993.580117.
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1992 | Conference Paper | LibreCat-ID: 13016
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” in IEEE International Test Conference (ITC’92), 1992, pp. 120–129, doi: 10.1109/test.1992.527812.
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1990 | Conference Paper | LibreCat-ID: 13018
S. Hellebrand and H.-J. Wunderlich, “Tools and Devices Supporting the Pseudo-Exhaustive Test,” in European Design Automation Conference (EDAC’90), 1990, pp. 13–17, doi: 10.1109/edac.1990.136612.
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1990 | Conference Paper | LibreCat-ID: 13019
S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,” in IEEE International Test Conference (ITC’90), 1990, pp. 670–679, doi: 10.1109/test.1990.114082.
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1989 | Conference Paper | LibreCat-ID: 13020
H.-J. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,” in IEEE International Test Conference (ITC’89), 1989, pp. 19–27, doi: 10.1109/test.1989.82273.
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1988 | Conference Paper | LibreCat-ID: 13021
H.-J. Wunderlich and S. Hellebrand, “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits,” in 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi: 10.1109/ftcs.1988.5294.
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1988 | Conference Paper | LibreCat-ID: 13058
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, and A. Kunzmann, “Integrated Tools for Automatic Design for Testability,” in Tool Integration and Design Environments, F.J. Rammig (Editor), 1988, pp. 233–258.
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1988 | Conference Paper | LibreCat-ID: 13062
S. Hellebrand and H.-J. Wunderlich, “Automatisierung des Entwurfs vollständig testbarer Schaltungen,” in GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 1988, pp. 145–159.
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