151 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2024 | Misc | LibreCat-ID: 50284
Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.
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2024 | Misc | LibreCat-ID: 51799
Ustimova M, Sadeghi-Kohan S, Hellebrand S. Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.
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2023 | Misc | LibreCat-ID: 35204
Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.
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2023 | Conference Paper | LibreCat-ID: 41875
Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing: Balancing Performance, Power, Reliability, and Safety. In: 28th IEEE European Test Symposium (ETS’23), May 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056
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2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.
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2023 | Journal Article | LibreCat-ID: 46264
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
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2022 | Misc | LibreCat-ID: 29890
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
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2020 | Misc | LibreCat-ID: 15419
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591
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2020 | Conference Paper | LibreCat-ID: 19421
Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
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2019 | Misc | LibreCat-ID: 8112
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.
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2018 | Misc | LibreCat-ID: 4576
Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133.
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020
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2018 | Conference Paper | LibreCat-ID: 10575
Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933
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2017 | Misc | LibreCat-ID: 13078
Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz.; 2017.
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). IEEE; 2017. doi:10.1109/ddecs.2017.7934564
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26
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2015 | Journal Article | LibreCat-ID: 13056
Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359.
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2015 | Misc | LibreCat-ID: 13077
Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany; 2015.
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2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014. doi:10.1109/test.2014.7035360
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2014 | Journal Article | LibreCat-ID: 13054
Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (it). 2014;56(4):165-172.
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2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA). 2014;30(5):527-540.
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand S. Analyzing and Quantifying Fault Tolerance Properties. In: 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE; 2013. doi:10.1109/latw.2013.6562662
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2013 | Misc | LibreCat-ID: 13075
Cook A, Rodriguez Gomez L, Hellebrand S, Indlekofer T, Wunderlich H-J. Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina; 2013.
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2012 | Conference Paper | LibreCat-ID: 12980
Cook A, Hellebrand S, E. Imhof M, Mumtaz A, Wunderlich H-J. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In: 13th IEEE Latin American Test Workshop (LATW’12). Quito, Ecuador: IEEE; 2012:1-4. doi:10.1109/latw.2012.6261229
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2012 | Conference Paper | LibreCat-ID: 12981
Cook A, Hellebrand S, Wunderlich H-J. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In: 17th IEEE European Test Symposium (ETS’12). Annecy, France: IEEE; 2012:1-6. doi:10.1109/ets.2012.6233025
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2012 | Misc | LibreCat-ID: 13074
Cook A, Hellebrand S, Wunderlich H-J. Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany; 2012.
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2011 | Conference Paper | LibreCat-ID: 12982
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Diagnostic Test of Robust Circuits. In: 20th IEEE Asian Test Symposium (ATS’11). New Delhi, India: IEEE; 2011:285-290. doi:10.1109/ats.2011.55
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2011 | Conference Paper | LibreCat-ID: 12984
Polian I, Becker B, Hellebrand S, Wunderlich H-J, Maxwell P. Towards Variation-Aware Test Methods. In: 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE; 2011. doi:10.1109/ets.2011.51
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2011 | Conference Paper | LibreCat-ID: 13053
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Robuster Selbsttest mit Diagnose. In: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf.” Hamburg, Germany; 2011:48-53.
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2011 | Journal Article | LibreCat-ID: 13052
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer. 2011;54(4):1813-1826.
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2010 | Misc | LibreCat-ID: 10670
Fröse V, Ibers R, Hellebrand S. Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany; 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE; 2010. doi:10.1109/dsnw.2010.5542612
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2010 | Conference Paper | LibreCat-ID: 13051
Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.
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2010 | Misc | LibreCat-ID: 13073
Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19
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2010 | Conference Paper | LibreCat-ID: 12988
Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570
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2010 | Conference Paper | LibreCat-ID: 13049
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.
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2008 | Misc | LibreCat-ID: 13033
Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.
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2008 | Misc | LibreCat-ID: 13035
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
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2007 | Misc | LibreCat-ID: 13038
Hellebrand S. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk); 2007.
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2007 | Misc | LibreCat-ID: 13039
Ali M, Welzl M, Hessler S, Hellebrand S. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007.
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2007 | Misc | LibreCat-ID: 13042
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand S. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07). IEEE; 2007:50-58. doi:10.1109/dft.2007.43
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07). IEEE; 2007:185-190. doi:10.1109/ddecs.2007.4295278
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. In: 12th IEEE European Test Symposium (ETS’07). IEEE; 2007:91-96. doi:10.1109/ets.2007.10
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. In: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper). ; 2007.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper). 2007;37(4 (124)):212-219.
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2007 | Journal Article | LibreCat-ID: 13044
Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture. 2007;1(2):113-123.
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2007 | Conference Paper | LibreCat-ID: 13040
Ali M, Welzl M, Hessler S, Hellebrand S. A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. In: 4th International Conference on Information Technology: New Generations (ITNG’07). ; 2007:1027-1032.
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2007 | Conference Paper | LibreCat-ID: 13041
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. Test und Zuverlässigkeit nanoelektronischer Systeme. In: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2007.
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2006 | Journal Article | LibreCat-ID: 13045
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. it - Information Technology. 2006;48(5):305-311.
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2005 | Misc | LibreCat-ID: 13101
Ali M, Welzl M, Hellebrand S. Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
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2005 | Misc | LibreCat-ID: 13102
Oehler P, Hellebrand S. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
Ali M, Welzl M, Zwicknagl M, Hellebrand S. Considerations for Fault-Tolerant Networks on Chips. In: IEEE International Conference on Microelectronics (ICM’05). IEEE; 2005. doi:10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler P, Hellebrand S. Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In: 10th IEEE European Test Symposium (ETS’05). IEEE; 2005:148-153. doi:10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali M, Welzl M, Hellebrand S. A Dynamic Routing Mechanism for Network on Chip. In: 23rd IEEE NORCHIP Conference. IEEE; 2005:70-73. doi:10.1109/norchp.2005.1596991
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2004 | Misc | LibreCat-ID: 13099
Breu R, Fahringer T, Fensel D, Hellebrand S, Middeldorp A, Scherzer O. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. OCG Journal, pp. 28-29; 2004.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand S, Wuertenberger A, S. Tautermann C. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France; 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357
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2003 | Misc | LibreCat-ID: 13098
Breu R, Hellebrand S, Welzl M. Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia; 2003.
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870
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| DOI
2002 | Misc | LibreCat-ID: 13097
Hellebrand S, Wuertenberger A. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA; 2002.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700
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| DOI
2002 | Journal Article | LibreCat-ID: 13069
Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.
LibreCat
2002 | Journal Article | LibreCat-ID: 13070
Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.
LibreCat
2001 | Misc | LibreCat-ID: 13096
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden; 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712
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| DOI
2001 | Journal Article | LibreCat-ID: 13047
Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.
LibreCat
2001 | Journal Article | LibreCat-ID: 13068
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.
LibreCat
2000 | Misc | LibreCat-ID: 13094
Hellebrand S, Wunderlich H-J. Hardwarepraktikum Im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag; 2000.
LibreCat
2000 | Misc | LibreCat-ID: 13095
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal; 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274
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| DOI
1999 | Book | LibreCat-ID: 13065
Hellebrand S. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg; 1999.
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1999 | Misc | LibreCat-ID: 13093
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop; 1999.
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693
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| DOI
1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.
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1998 | Report | LibreCat-ID: 13029
Hellebrand S, Wunderlich H-J. Test Und Synthese Schneller Eingebetteter Systeme. Universität Stuttgart; 1998.
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1998 | Misc | LibreCat-ID: 13091
N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1998.
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1998 | Misc | LibreCat-ID: 13092
N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop; 1998.
LibreCat
1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: Mixed-Mode BIST Using Embedded Processors. 5. Kluwer Academic Publishers; 1998.
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1998 | Journal Article | LibreCat-ID: 13061
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA. 1998;12(1/2):127-138.
LibreCat
1998 | Journal Article | LibreCat-ID: 13064
Hellebrand S, Hertwig A, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test. 1998;15(4):36-41.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig A, Hellebrand S, Wunderlich H-J. Fast Self-Recovering Controllers. In: 16th IEEE VLSI Test Symposium (VTS’98). IEEE; 1998:296-302. doi:10.1109/vtest.1998.670883
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| DOI
1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In: Design Automation and Test in Europe (DATE’98). ; 1998:173-179. doi:10.1109/date.1998.655853
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| DOI
1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik V, V. Klimets Y, Hellebrand S, Wunderlich H-J. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98). ; 1998:27-33.
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1997 | Misc | LibreCat-ID: 13089
Tsai K-H, Hellebrand S, Rajski J, Marek-Sadowska M. STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1997.
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1997 | Misc | LibreCat-ID: 13090
Hertwig A, Hellebrand S, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece; 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194
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| DOI
1996 | Misc | LibreCat-ID: 13087
Hellebrand S, Wunderlich H-J. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1996.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France; 1996.
LibreCat
1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962
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| DOI
1995 | Report | LibreCat-ID: 13026
Hellebrand S, Wunderlich H-J. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany; 1995.
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1995 | Report | LibreCat-ID: 13027
Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany; 1995.
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1995 | Report | LibreCat-ID: 13028
Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.
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1995 | Misc | LibreCat-ID: 13086
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534
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| DOI
1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997
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| DOI
1994 | Report | LibreCat-ID: 13024
Hellebrand S, Juergensen A, Wunderlich H-J. Synthesis for Off-Line Testability. University of Siegen, Germany; 1994.
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1994 | Report | LibreCat-ID: 13025
Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
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1994 | Misc | LibreCat-ID: 13083
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13084
Hellebrand S, Wunderlich H-J. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13085
Hellebrand S, Paulo Teixeira J, Wunderlich H-J. Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752
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| DOI
1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815
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| DOI
1993 | Misc | LibreCat-ID: 13081
Hellebrand S, Tarnick S, Rajski J, Courtois B. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.
LibreCat
1993 | Misc | LibreCat-ID: 13082
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). IEEE; 1993. doi:10.1109/iccad.1993.580117
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| DOI
1992 | Report | LibreCat-ID: 13023
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France; 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13076
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA; 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13080
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada; 1992.
LibreCat
1992 | Journal Article | LibreCat-ID: 13017
Wunderlich H-J, Hellebrand S. The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 1992;11(1):26-33. doi:10.1109/43.108616
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| DOI
1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. In: IEEE International Test Conference (ITC’92). IEEE; 1992:120-129. doi:10.1109/test.1992.527812
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| DOI
1991 | Book | LibreCat-ID: 13034
Hellebrand S. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag; 1991.
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1990 | Misc | LibreCat-ID: 13103
Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA; 1990.
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1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand S, Wunderlich H-J. Tools and Devices Supporting the Pseudo-Exhaustive Test. In: European Design Automation Conference (EDAC’90). IEEE; 1990:13-17. doi:10.1109/edac.1990.136612
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| DOI
1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. In: IEEE International Test Conference (ITC’90). IEEE; 1990:670-679. doi:10.1109/test.1990.114082
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| DOI
1989 | Conference Paper | LibreCat-ID: 13020
Wunderlich H-J, Hellebrand S. The Pseudo-Exhaustive Test of Sequential Circuits. In: IEEE International Test Conference (ITC’89). IEEE; 1989:19-27. doi:10.1109/test.1989.82273
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| DOI
1988 | Conference Paper | LibreCat-ID: 13021
Wunderlich H-J, Hellebrand S. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. In: 18th International Symposium on Fault-Tolerant Computing, FTCS-18. ; 1988:36-45. doi:10.1109/ftcs.1988.5294
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| DOI
1988 | Conference Paper | LibreCat-ID: 13058
Schmid D, Wunderlich H-J, Feldbusch F, Hellebrand S, Holzinger J, Kunzmann A. Integrated Tools for Automatic Design for Testability. In: Tool Integration and Design Environments, F.J. Rammig (Editor). Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP; 1988:233-258.
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1988 | Conference Paper | LibreCat-ID: 13062
Hellebrand S, Wunderlich H-J. Automatisierung des Entwurfs vollständig testbarer Schaltungen. In: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188. Springer Verlag; 1988:145-159.
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1986 | Report | LibreCat-ID: 13022
Hellebrand S. Deformation Dicker Punkte Und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany; 1986.
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151 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.
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2024 | Misc | LibreCat-ID: 50284
Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.
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2024 | Misc | LibreCat-ID: 51799
Ustimova M, Sadeghi-Kohan S, Hellebrand S. Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.
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2023 | Misc | LibreCat-ID: 35204
Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.
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2023 | Conference Paper | LibreCat-ID: 41875
Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing: Balancing Performance, Power, Reliability, and Safety. In: 28th IEEE European Test Symposium (ETS’23), May 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056
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| DOI
2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.
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2023 | Journal Article | LibreCat-ID: 46264
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
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| DOI
| Download (ext.)
2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
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| DOI
2022 | Misc | LibreCat-ID: 29890
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
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2020 | Misc | LibreCat-ID: 15419
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591
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| DOI
2020 | Conference Paper | LibreCat-ID: 19421
Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
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2019 | Misc | LibreCat-ID: 8112
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
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| DOI
2019 | Journal Article | LibreCat-ID: 13048
Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.
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2018 | Misc | LibreCat-ID: 4576
Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942
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| DOI
2018 | Journal Article | LibreCat-ID: 13057
Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133.
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020
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| DOI
2018 | Conference Paper | LibreCat-ID: 10575
Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028
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| DOI
2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933
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| DOI
2017 | Misc | LibreCat-ID: 13078
Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz.; 2017.
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). IEEE; 2017. doi:10.1109/ddecs.2017.7934564
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| DOI
2016 | Conference Paper | LibreCat-ID: 12975
Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20
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| DOI
2015 | Conference Paper | LibreCat-ID: 12976
Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26
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| DOI
2015 | Journal Article | LibreCat-ID: 13056
Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359.
LibreCat
2015 | Misc | LibreCat-ID: 13077
Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany; 2015.
LibreCat
2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014. doi:10.1109/test.2014.7035360
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| DOI
2014 | Journal Article | LibreCat-ID: 13054
Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (it). 2014;56(4):165-172.
LibreCat
2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA). 2014;30(5):527-540.
LibreCat
2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand S. Analyzing and Quantifying Fault Tolerance Properties. In: 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE; 2013. doi:10.1109/latw.2013.6562662
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| DOI
2013 | Misc | LibreCat-ID: 13075
Cook A, Rodriguez Gomez L, Hellebrand S, Indlekofer T, Wunderlich H-J. Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina; 2013.
LibreCat
2012 | Conference Paper | LibreCat-ID: 12980
Cook A, Hellebrand S, E. Imhof M, Mumtaz A, Wunderlich H-J. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In: 13th IEEE Latin American Test Workshop (LATW’12). Quito, Ecuador: IEEE; 2012:1-4. doi:10.1109/latw.2012.6261229
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| DOI
2012 | Conference Paper | LibreCat-ID: 12981
Cook A, Hellebrand S, Wunderlich H-J. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In: 17th IEEE European Test Symposium (ETS’12). Annecy, France: IEEE; 2012:1-6. doi:10.1109/ets.2012.6233025
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| DOI
2012 | Misc | LibreCat-ID: 13074
Cook A, Hellebrand S, Wunderlich H-J. Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany; 2012.
LibreCat
2011 | Conference Paper | LibreCat-ID: 12982
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Diagnostic Test of Robust Circuits. In: 20th IEEE Asian Test Symposium (ATS’11). New Delhi, India: IEEE; 2011:285-290. doi:10.1109/ats.2011.55
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| DOI
2011 | Conference Paper | LibreCat-ID: 12984
Polian I, Becker B, Hellebrand S, Wunderlich H-J, Maxwell P. Towards Variation-Aware Test Methods. In: 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE; 2011. doi:10.1109/ets.2011.51
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| DOI
2011 | Conference Paper | LibreCat-ID: 13053
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Robuster Selbsttest mit Diagnose. In: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf.” Hamburg, Germany; 2011:48-53.
LibreCat
2011 | Journal Article | LibreCat-ID: 13052
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer. 2011;54(4):1813-1826.
LibreCat
2010 | Misc | LibreCat-ID: 10670
Fröse V, Ibers R, Hellebrand S. Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany; 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 12987
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE; 2010. doi:10.1109/dsnw.2010.5542612
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| DOI
2010 | Conference Paper | LibreCat-ID: 13051
Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.
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2010 | Misc | LibreCat-ID: 13073
Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24
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| DOI
2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648
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| DOI
2010 | Conference Paper | LibreCat-ID: 12986
Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19
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| DOI
2010 | Conference Paper | LibreCat-ID: 12988
Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570
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| DOI
2010 | Conference Paper | LibreCat-ID: 13049
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.
LibreCat
2009 | Conference Paper | LibreCat-ID: 12991
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027
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| DOI
2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28
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| DOI
2009 | Conference Paper | LibreCat-ID: 13030
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.
LibreCat
2008 | Misc | LibreCat-ID: 13033
Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.
LibreCat
2008 | Misc | LibreCat-ID: 13035
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.
LibreCat
2008 | Conference Paper | LibreCat-ID: 12992
Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30
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| DOI
2008 | Conference Paper | LibreCat-ID: 12994
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34
LibreCat
| DOI
2008 | Conference Paper | LibreCat-ID: 12993
Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32
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| DOI
2008 | Conference Paper | LibreCat-ID: 13031
Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
LibreCat
2008 | Conference Paper | LibreCat-ID: 13032
Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.
LibreCat
2007 | Misc | LibreCat-ID: 13038
Hellebrand S. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk); 2007.
LibreCat
2007 | Misc | LibreCat-ID: 13039
Ali M, Welzl M, Hessler S, Hellebrand S. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007.
LibreCat
2007 | Misc | LibreCat-ID: 13042
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.
LibreCat
2007 | Misc | LibreCat-ID: 13043
Hellebrand S. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.
LibreCat
2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07). IEEE; 2007:50-58. doi:10.1109/dft.2007.43
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| DOI
2007 | Conference Paper | LibreCat-ID: 12996
Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07). IEEE; 2007:185-190. doi:10.1109/ddecs.2007.4295278
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| DOI
2007 | Conference Paper | LibreCat-ID: 12997
Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. In: 12th IEEE European Test Symposium (ETS’07). IEEE; 2007:91-96. doi:10.1109/ets.2007.10
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| DOI
2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. In: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper). ; 2007.
LibreCat
2007 | Journal Article | LibreCat-ID: 13036
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper). 2007;37(4 (124)):212-219.
LibreCat
2007 | Journal Article | LibreCat-ID: 13044
Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture. 2007;1(2):113-123.
LibreCat
2007 | Conference Paper | LibreCat-ID: 13040
Ali M, Welzl M, Hessler S, Hellebrand S. A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. In: 4th International Conference on Information Technology: New Generations (ITNG’07). ; 2007:1027-1032.
LibreCat
2007 | Conference Paper | LibreCat-ID: 13041
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. Test und Zuverlässigkeit nanoelektronischer Systeme. In: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2007.
LibreCat
2006 | Journal Article | LibreCat-ID: 13045
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. it - Information Technology. 2006;48(5):305-311.
LibreCat
2005 | Misc | LibreCat-ID: 13101
Ali M, Welzl M, Hellebrand S. Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
LibreCat
2005 | Misc | LibreCat-ID: 13102
Oehler P, Hellebrand S. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.
LibreCat
2005 | Conference Paper | LibreCat-ID: 12999
Ali M, Welzl M, Zwicknagl M, Hellebrand S. Considerations for Fault-Tolerant Networks on Chips. In: IEEE International Conference on Microelectronics (ICM’05). IEEE; 2005. doi:10.1109/icm.2005.1590063
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| DOI
2005 | Conference Paper | LibreCat-ID: 13000
Oehler P, Hellebrand S. Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In: 10th IEEE European Test Symposium (ETS’05). IEEE; 2005:148-153. doi:10.1109/ets.2005.28
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| DOI
2005 | Conference Paper | LibreCat-ID: 12998
Ali M, Welzl M, Hellebrand S. A Dynamic Routing Mechanism for Network on Chip. In: 23rd IEEE NORCHIP Conference. IEEE; 2005:70-73. doi:10.1109/norchp.2005.1596991
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| DOI
2004 | Misc | LibreCat-ID: 13099
Breu R, Fahringer T, Fensel D, Hellebrand S, Middeldorp A, Scherzer O. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. OCG Journal, pp. 28-29; 2004.
LibreCat
2004 | Misc | LibreCat-ID: 13100
Hellebrand S, Wuertenberger A, S. Tautermann C. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France; 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357
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| DOI
2003 | Misc | LibreCat-ID: 13098
Breu R, Hellebrand S, Welzl M. Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia; 2003.
LibreCat
2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870
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| DOI
2002 | Misc | LibreCat-ID: 13097
Hellebrand S, Wuertenberger A. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA; 2002.
LibreCat
2002 | Journal Article | LibreCat-ID: 13003
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700
LibreCat
| DOI
2002 | Journal Article | LibreCat-ID: 13069
Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.
LibreCat
2002 | Journal Article | LibreCat-ID: 13070
Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.
LibreCat
2001 | Misc | LibreCat-ID: 13096
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden; 2001.
LibreCat
2001 | Conference Paper | LibreCat-ID: 13004
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712
LibreCat
| DOI
2001 | Journal Article | LibreCat-ID: 13047
Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.
LibreCat
2001 | Journal Article | LibreCat-ID: 13068
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.
LibreCat
2000 | Misc | LibreCat-ID: 13094
Hellebrand S, Wunderlich H-J. Hardwarepraktikum Im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag; 2000.
LibreCat
2000 | Misc | LibreCat-ID: 13095
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal; 2000.
LibreCat
2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274
LibreCat
| DOI
1999 | Book | LibreCat-ID: 13065
Hellebrand S. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg; 1999.
LibreCat
1999 | Misc | LibreCat-ID: 13093
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop; 1999.
LibreCat
1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693
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| DOI
1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.
LibreCat
1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.
LibreCat
1998 | Report | LibreCat-ID: 13029
Hellebrand S, Wunderlich H-J. Test Und Synthese Schneller Eingebetteter Systeme. Universität Stuttgart; 1998.
LibreCat
1998 | Misc | LibreCat-ID: 13091
N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1998.
LibreCat
1998 | Misc | LibreCat-ID: 13092
N. Yarmolik V, Hellebrand S, Wunderlich H-J. Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop; 1998.
LibreCat
1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: Mixed-Mode BIST Using Embedded Processors. 5. Kluwer Academic Publishers; 1998.
LibreCat
1998 | Journal Article | LibreCat-ID: 13061
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA. 1998;12(1/2):127-138.
LibreCat
1998 | Journal Article | LibreCat-ID: 13064
Hellebrand S, Hertwig A, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test. 1998;15(4):36-41.
LibreCat
1998 | Conference Paper | LibreCat-ID: 13007
Hertwig A, Hellebrand S, Wunderlich H-J. Fast Self-Recovering Controllers. In: 16th IEEE VLSI Test Symposium (VTS’98). IEEE; 1998:296-302. doi:10.1109/vtest.1998.670883
LibreCat
| DOI
1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In: Design Automation and Test in Europe (DATE’98). ; 1998:173-179. doi:10.1109/date.1998.655853
LibreCat
| DOI
1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik V, V. Klimets Y, Hellebrand S, Wunderlich H-J. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98). ; 1998:27-33.
LibreCat
1997 | Misc | LibreCat-ID: 13089
Tsai K-H, Hellebrand S, Rajski J, Marek-Sadowska M. STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1997.
LibreCat
1997 | Misc | LibreCat-ID: 13090
Hertwig A, Hellebrand S, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece; 1997.
LibreCat
1997 | Conference Paper | LibreCat-ID: 13009
Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194
LibreCat
| DOI
1996 | Misc | LibreCat-ID: 13087
Hellebrand S, Wunderlich H-J. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1996.
LibreCat
1996 | Misc | LibreCat-ID: 13088
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France; 1996.
LibreCat
1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962
LibreCat
| DOI
1995 | Report | LibreCat-ID: 13026
Hellebrand S, Wunderlich H-J. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany; 1995.
LibreCat
1995 | Report | LibreCat-ID: 13027
Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany; 1995.
LibreCat
1995 | Report | LibreCat-ID: 13028
Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.
LibreCat
1995 | Misc | LibreCat-ID: 13086
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995.
LibreCat
1995 | Journal Article | LibreCat-ID: 13011
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534
LibreCat
| DOI
1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997
LibreCat
| DOI
1994 | Report | LibreCat-ID: 13024
Hellebrand S, Juergensen A, Wunderlich H-J. Synthesis for Off-Line Testability. University of Siegen, Germany; 1994.
LibreCat
1994 | Report | LibreCat-ID: 13025
Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13083
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13084
Hellebrand S, Wunderlich H-J. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13085
Hellebrand S, Paulo Teixeira J, Wunderlich H-J. Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752
LibreCat
| DOI
1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815
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| DOI
1993 | Misc | LibreCat-ID: 13081
Hellebrand S, Tarnick S, Rajski J, Courtois B. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.
LibreCat
1993 | Misc | LibreCat-ID: 13082
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). IEEE; 1993. doi:10.1109/iccad.1993.580117
LibreCat
| DOI
1992 | Report | LibreCat-ID: 13023
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France; 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13076
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA; 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13080
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada; 1992.
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1992 | Journal Article | LibreCat-ID: 13017
Wunderlich H-J, Hellebrand S. The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 1992;11(1):26-33. doi:10.1109/43.108616
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| DOI
1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. In: IEEE International Test Conference (ITC’92). IEEE; 1992:120-129. doi:10.1109/test.1992.527812
LibreCat
| DOI
1991 | Book | LibreCat-ID: 13034
Hellebrand S. Synthese Vollständig Testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag; 1991.
LibreCat
1990 | Misc | LibreCat-ID: 13103
Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA; 1990.
LibreCat
1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand S, Wunderlich H-J. Tools and Devices Supporting the Pseudo-Exhaustive Test. In: European Design Automation Conference (EDAC’90). IEEE; 1990:13-17. doi:10.1109/edac.1990.136612
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| DOI
1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. In: IEEE International Test Conference (ITC’90). IEEE; 1990:670-679. doi:10.1109/test.1990.114082
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| DOI
1989 | Conference Paper | LibreCat-ID: 13020
Wunderlich H-J, Hellebrand S. The Pseudo-Exhaustive Test of Sequential Circuits. In: IEEE International Test Conference (ITC’89). IEEE; 1989:19-27. doi:10.1109/test.1989.82273
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| DOI
1988 | Conference Paper | LibreCat-ID: 13021
Wunderlich H-J, Hellebrand S. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. In: 18th International Symposium on Fault-Tolerant Computing, FTCS-18. ; 1988:36-45. doi:10.1109/ftcs.1988.5294
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| DOI
1988 | Conference Paper | LibreCat-ID: 13058
Schmid D, Wunderlich H-J, Feldbusch F, Hellebrand S, Holzinger J, Kunzmann A. Integrated Tools for Automatic Design for Testability. In: Tool Integration and Design Environments, F.J. Rammig (Editor). Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP; 1988:233-258.
LibreCat
1988 | Conference Paper | LibreCat-ID: 13062
Hellebrand S, Wunderlich H-J. Automatisierung des Entwurfs vollständig testbarer Schaltungen. In: GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188. Springer Verlag; 1988:145-159.
LibreCat
1986 | Report | LibreCat-ID: 13022
Hellebrand S. Deformation Dicker Punkte Und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany; 1986.
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